Sherman M. Dance

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A double-precision multiplier for floating-point and media-streaming instructions in the first-generation CELL processor [1] on 90nm PD/SOI is reported. Multiplication by recoding and successive partial-product (PP) compression is completed in three 11FO4 cycles including merging with the aligner. Figure 20.3.3 shows the micro-architecture of the design. At(More)
This paper describes the design and implementation of the vector scalar unit (VSU) in the first-generation CELL processor. VSU executes floating-point and vector media extension instructions. VSU contains 1.7 million transistors and occupies an area of 3.1 mm/sup 2/ in a 90nm PD-SOI technology. Extensive static and dynamic circuit techniques are used to(More)
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