In this paper, we propose an asynchronous wrapper with novel handshake circuits for data communication to be used in GALS systems. The handshake circuits include two communication ports and a local clock controller. We present two approaches for the implementation of communication ports; one with pure standard cells and the other with Müller C elements.The… (More)
In this paper we discuss some aspects of designing low power asynchronous wrappers for use in GALS based communication systems. We propose a general method for designing asynchronous wrappers for use in asynchro-nous multiport-to-multiport communication channels with low swing busses and variable power supply voltages .
The GALS (Globally Asynchronous Locally Synchronous) approach is highly suitable for implementation of communication systems. In this paper we describe an efficient design flow for GALS design based on commercial tools. As design example we have selected a digital FIR filter. It is a nontrivial task to develop an efficient design flow for GALS based systems… (More)
In this paper, we propose an asynchronous wrapper with new handshake circuits for the data communication in GALS systems. The handshake circuits include two data-ports and a local clock controller. we present two approaches for the implementation of data-ports; one with pure standard cells and the other with Muller-C elements.The detailed design methodology… (More)
In this paper, we propose a VLSI implementation method for one-dimensional discrete wavelet transform (1D-DWT) based on the GALS systems approach. An asynchronous wrapper, which includes two data communication ports and a local clock controller, is designed for the asynchronous data communication between the locally synchronous filtering modules in the… (More)
In this paper, we propose a pipeline scheme for efficient realization of a complex multiplier using distributed arithmetic. The pipelined multiplier consists of one conventional multiplier that is multiplexed and some small additional circuitry on the boundary. The proposed scheme reduces the chip area as well as the interconnec-tions by nearly half… (More)