Shengcheng Wang

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The manufacturing yield challenge of three-dimensional integrated circuit (3D ICs) is one of the key obstacles in the industry adoption of 3D integration based on through-silicon-vias (TSVs). The addition of spare TSVs to repair faulty functional TSVs is an effective method for yield and reliability enhancement, but this approach results in significant(More)
In recent years, interconnect issues emerged as major performance challenges for Two-Dimensional-Integrated-Circuits (2D-ICs). In this context, Three-Dimensional-ICs (3D-ICs), which consist of several active layers stacked above each other, offer a very attractive alternative to conventional 2D-ICs. However, 3D-ICs also face many challenges associated with(More)
Electromigration (EM) occurrence on through-silicon-vias (TSVs) is a major reliability concern for Three-Dimensional Integrated-Circuits (3D ICs), and EM can severely reduce the mean-time-to-failure (MTTF). In this work, a novel fault tolerant technique is proposed to increase the MTTF of the functional TSV network through the assignment of spare TSVs to(More)
Power/Ground (P/G) Through-Silicon-Vias (TSVs) in the Power Distribution Network (PDN) of Three-Dimensional-Integrated-Circuit (3D-IC) have a twofold impact on the delays of the surrounding gates. TSV fabrication causes thermal stress around TSVs, which results in significant carrier mobility variations in their vicinity. On the other hand, the insertion of(More)
Electromigration (EM) becomes a major reliability concern in three-dimensional integrated-circuits (3D ICs). To mitigate this problem, a typical solution is to use TSV redundancy in a reactive manner, maintaining the operability of a 3D chip in the presence of EM failures by detecting and replacing faulty TSVs with spares. In this work, we explore an(More)
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