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—Gate-level characterization (GLC) is the process of quantifying physical and manifestational properties for each gate of an integrated circuit (IC). It is a key step in many IC applications that target cryptography, security, digital rights management, low power, and yield optimization. However, GLC is a challenging task due to the size and structure of(More)
Gate-level characterization (GLC) is the process of characterizing each gate of an integrated circuit (IC) in terms of its physical and manifestation properties. It is a key step in the IC applications regarding cryptography, security, and digital rights management. However, GLC is challenging due to the existence of manufacturing variability (MV) and the(More)
BACKGROUND Telomeres play a key role in the maintenance of chromosome integrity and stability, and telomere shortening is involved in initiation and progression of malignancies. A series of epidemiological studies have examined the association between shortened telomeres and risk of cancers, but the findings remain conflicting. METHODS A dataset composed(More)
We have developed an ultra low power (well below 1 nano-joule per transaction), ultra high speed (less than 1 nanosecond), and low cost (a few hundred gates) public physically unclonable function (PPUF). We have also developed the first PPUF-based smart card (SC). We analyze and demonstrate the security of this new SC against several families of potential(More)
Recently μ opioid receptor (MOR) has been shown to be closely associated with depression. Here we investigated the action of Shuyu, a Chinese herbal prescription, on repeated restraint stress induced depression-like rats, with specific attention to the role of MOR and the related signal cascade. Our results showed that repeated restraint stress caused(More)
This paper proposes Hardware Trojan (HT) placement techniques that yield challenging HT detection benchmarks. We develop three types of one-gate HT benchmarks based on switching power, leakage power, and delay measurements that are commonly used in HT detection. In particular, we employ an iterative searching algorithm to find rarely switching locations, an(More)
Hardware Trojans (HTs) pose a significant threat to the modern and pending integrated circuit (IC). Several approaches have been proposed to detect HTs, but they are either incapable of detecting HTs under the presence of process variation (PV) or unable to handle very large circuits in the modern IC industry. We develop a scalable HT detection and(More)