Shen-Iuan Liu

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An ultra-wideband (UWB) noise-canceling low-noise amplifier (LNA) is presented. By using inductive series and shunt peaking techniques, the effective bandwidth of noise canceling is extended. This LNA has been fabricated in a 0.18/spl mu/m CMOS process. The measured noise figure is 4.5-5.1dB over 3.1-10.6-GHz, while the power gain is 9.7dB with a -3-dB(More)
A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge(More)
A successive approximation register-controlled delay-locked loop (SARDLL) has been fabricated in a 0.25m standard n-well DPTM CMOS process to realize a fast-lock clock-deskew buffer for long distance clock distribution. This DLL adopts a binary search method to shorten lock time while maintaining tight synchronization between input and output clocks. The(More)
An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18m CMOS technology. The measured duty-cycle error is between 1.5% and 1 4% for the input duty cycle of 40% 60%. The measured peak-to-peak jitter(More)
A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using(More)
A 0.5–5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. The charge pump current is also calibrated to reduce the static phase error. This MDLL has been fabricated in 0.13m CMOS process.(More)
A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition,(More)