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In this brief, we propose an effective adaptation of viability analysis in statistical static timing analysis. The adaption benefits well from a dynamic programming implementation of the viability… (More)
UT Mixed-Signal Simulator is a mixed-signal, mixeddomain, and mixed-language design environment which supports VHDL-AMS 1999, VHDL-2002, Verilog 2001, SystemVerilog 2005 assertions, and SystemC 2005.
For design of today’s large digital systems, a modeling approach for early exploration of different possible architectures is useful. The modeling approach should be fast, simple and powerful to… (More)