Shay Michaely

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The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing(More)
The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of processing technology, because wire resistance and cross capacitances become more important with scaling. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the total area(More)
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