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This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions(More)
Designing reliable CMOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrie:r effects. This paper considers logic synthesis to handle electromigration and hot carrier degradation early in the design. phase. The electromigration and the hot carier effects are(More)
LAPLUS is a novel switch algorithm for flow control of the Available Bit Rate (ABR) Asynchronous Transfer Mode (ATM) service. It ensures a steady-state rate allocation satisfying the MCR-plus-equal-share criterion. It only requires constant-time processing and two tags to be stored per flow. It is naturally able to take Peak Cell Rates of flows into(More)
Designing reliable CbfOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrier effects. This paper considers logic synthesis to handle electromigra-tion and hot carrier degmdation early in the design phase. The electromigration and the hot carier eflecls are(More)
Designing reliable CMOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrier eects. This paper considers logic synthesis to handle electromigra-tion and hot carrier degradation early in the design phase. The electromigration and the hot carier eects are estimated(More)
This paper presents accurate estimation of signal activity a t the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions(More)