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Recommended Citation Jha, Sharada. "Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults." PhD ABSTRACT With rapid advancement in science and technology and decreasing feature size of transistors, the complexity of VLSI designs is constantly increasing. With increasing density and complexity of the(More)
We propose a test-cube aware dynamic compaction method for reducing the test set size generated by scan ATPG. In the initial phase of ATPG, when the generated test cubes are significantly compatible, we start with a local cube merging approach. Then, we switch to a compacted cube-generation approach, when the compatibility of test cubes decrease. We propose(More)
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