Shaoyin Chen

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Strain engineering has become a workhorse in increasing charge carrier mobility to boost performance for sub-45nm CMOS logic technologies. While pFET transistors with embedded Si<inf>1&#x2212;x</inf>Ge<inf>x</inf> layers in the S/D region have been widely employed to induce compressive strain in the silicon channel, nFET transistors have mostly depended on(More)
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