Shaowen Qin

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Cache access latency and efficient usage of on-chip capacity are critical factors that affect the performance of the chip multiprocessor (CMP) architecture. In this paper, we propose a SPS2 cache architecture and cache coherence protocol for snooping-based CMP, in which each processor has both private and shared L2 cache to balance latency and capacity. Our(More)
The establishment of an existing practice scenario was an essential component in providing a basis for further research in the area of COTS software acquisition within the organisation. This report details the identification of means of describing the existing practice of software acquisition within an organisation and identification of models that could be(More)
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