Shaodi Gao

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Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and routability. A probabilistic model of interconnections enables designers to quickly predict routing congestion. We propose a powerful and fast estimation approach which allows wires to have(More)
In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent sub-problems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm(More)
We show that any n-net 2-terminal channel routing problem of density d can be wired on a two-layer grid of width w = d + 0 (d 1J3) when vertical wire segments are allowed to overlap for a distance of length 1. TItis is a considerable asymptotic improvement over the best known, and optimal, channel width of 2d-l for models in which no vertical overlap is(More)
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