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— The Internet is facing two problems simultaneously: there is a need for a faster switching/routing infrastructure, and a need to introduce guaranteed qualities of service (QoS). Each problem can be solved independently: switches and routers can be made faster by using input-queued crossbars, instead of shared memory systems; and QoS can be provided using(More)
Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to make efficient use of their expensive long-haul links. In this paper we consider how optics can be used to scale capacity and reduce power in a router. We start with the promising(More)
— The Internet is facing two problems simultaneously: there is a need for a faster switching/routing infrastructure, and a need to introduce guaranteed qualities of service (QoS). Each problem can be solved independently: switches and routers can be made faster by using input-queued crossbars, instead of shared memory systems; and QoS can be provided using(More)
— This paper is about high capacity switches and routers that give guaranteed throughput, rate and delay guarantees. Many routers are built using input queueing or combined input and output queueing (CIOQ), using crossbar switching fabrics. But such routers require impractically complex scheduling algorithms to provide the desired guarantees. We explore how(More)
A 32 x 32 synchronous crossbar chip was designed in a 0.27pm CMOS technology for use in a high-speed network switch [I]. The crossbar chip uses 32 Asymmetric Serial Links [2][3] to achieve high speed at the interfaces and to reduce both power and area. The crossbar switch core is implemented with static CMOS multi-stage multiplexors with multicast(More)
— The load-balanced switch architecture is a promising way to scale router capacity. It requires no centralized sched-uler, requires no memory operating faster than the line-rate, and can be built using a fixed, optical mesh. In a recent paper we explained how to prevent packet mis-sequencing and provide 100% throughput for all traffic patterns, and(More)
— This paper describes the design of a novel CMOS 2 Gb/s asymmetric serial link. The serial link is designed for systems that use high speed chip-to-chip communications. In such designs, power dissipation is a common problem, particularly when multiple serial links are required on one chip. The power arises primarily from the phase adjustment circuitry used(More)
This paper is an extended version of [1]. In conjunction with " A load-balanced switch with an arbitrary number of linecards " [2], it replaces " Architectures and algorithms for a load-balanced switch " [3]. Abstract— Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput(More)
— The Internet is facing two problems simultaneously: we need a faster switching/routing infrastructure, and we need to introduce guaranteed qualities of service (QoS). As a community, we have solutions to each: we can make the routers faster by using input-queued crossbars, instead of shared memory systems; and we can introduce QoS using WFQ-based packet(More)
Packet scheduling in switches is not programmable; operators only choose among a handful of scheduling algorithms implemented by the manufacturer. In contrast, other switch functions such as packet parsing and header processing are becoming programmable [10, 3, 6]. This paper presents a programmable packet scheduler that allows operators to program a(More)