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This paper presents a new CMOS image sensor (CIS) structure and ADC design for three-dimensional (3D) integrated imagers. A modular design of CIS sub-array is proposed with new readout and control scheme. It needs only one micro-bump (µbump) per sub-array, instead of per-pixel or per-column, to release the design rule restriction of the 3D stacking(More)
A lag-free CMOS image sensor (CIS) with Constant-Residue Reset (CRR) operation is presented in this paper. It effectively eliminates image lag effect caused by the channel doping profile variation of transfer transistor and non-optimized pixel layout in the 4T-pixel. A prototype 160×120 CMOS imager has been designed and fabricated in 0.18um 1P4M CIS(More)
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