Shan Chien Fang

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Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller Logic (PMRML) to overcome the glitch and Dissipation Timing Skew (DTS) problems in design of DPA-resistant cryptographic hardware. Both problems can significantly reduce the(More)
The allocation of device variables on I/O registers affects the code size and performance of an I/O device driver. This work seeks the allocation with the minimal software or hardware cost in a hardware/software codesign environment. The problems of exact minimization under constraints are formulated as zero-one integer linear programming problems.(More)
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