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- Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
- IEEE Trans. on Circuits and Systems
- 2013

Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive… (More)

- Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
- IEEE Trans. VLSI Syst.
- 2014

Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing… (More)

- Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny
- IEEE Trans. on Circuits and Systems
- 2015

Memristors are novel electrical devices used for a variety of applications including memory, logic circuits, and neuromorphic systems. Memristive technologies are attractive due to the nonvolatility, scalability, and compatibility with CMOS. Numerous physical experiments have shown the existence of a threshold voltage in some physical memristors.… (More)

Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) a hybrid CMOS-memristive logic family is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS inverters are added to… (More)

- Shahar Kvatinsky, Dmitry Belousov, +5 authors Uri C. Weiser
- IEEE Trans. on Circuits and Systems
- 2014

Copyright (c) 2014 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to pubs-permissions@ieee.org. Abstract— Memristors are passive components with a varying resistance which depends on the previous voltage applied across the device. While… (More)

- Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi
- 2013 IEEE International Symposium on Information…
- 2013

In a memristor crossbar array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this work, we study the sneak path problem in crossbars arrays, in which current can sneak through other cells,… (More)

- Daniel Soudry, Dotan Di Castro, Asaf Gal, Avinoam Kolodny, Shahar Kvatinsky
- IEEE Transactions on Neural Networks and Learning…
- 2015

Learning in multilayer neural networks (MNNs) relies on continuous updating of large matrices of synaptic weights by local rules. Such locality can be exploited for massive parallelism when implementing MNNs in hardware. However, these update rules require a multiply and accumulate operation for each synaptic weight, which is challenging to implement… (More)

- Yifat Levy, Jehoshua Bruck, +4 authors Shahar Kvatinsky
- Microelectronics Journal
- 2014

In-memory computation is one of the most promising features of memristive memory arrays. In this paper, we propose an array architecture that supports in-memory computation based on a logic array first proposed in 1972 by Sheldon Akers. The Akers logic array satisfies this objective since this array can realize any Boolean function, including bit sorting.… (More)

- Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar
- IEEE Computer Architecture Letters
- 2015

Associative Processor (AP) combines data storage and data processing, and functions simultaneously as a massively parallel array SIMD processor and memory. Traditionally, AP is based on CMOS technology, similar to other classes of massively parallel SIMD processors. The main component of AP is a Content Addressable Memory (CAM) array. As CMOS feature… (More)

- Eyal Rosenthal, Sergey Greshnikov, Daniel Soudry, Shahar Kvatinsky
- ISCAS
- 2016

In recent years, Neural Networks (NNs) have become widely popular for the execution of different machine learning algorithms. Training an NN is computationally intensive since it requires numerous multiplications of matrices that represent synaptic weights. It is therefore appealing to build a hardware-based NN accelerator to gain parallelism and efficient… (More)