Shabbir H. Batterywala

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Routing is one of the most complex stages in the back-end design process. Simple routing algorithms based on two stages of global routing and detailed routing do not offer appropriate opportunities to address problems arising from signal delay, cross-talk and process constraints. An intermediate stage of track assignment between global and detailed routing(More)
Dummy fills are being extensively used to enhance CMP planarity. However presence of these fills can have a significant impact on the values of interconnect capacitances. Accurate capacitance extraction accounting for these dummies is CPU intensive and cumbersome. For one, there are typically hundreds to thousands of dummy fills in a small layout region,(More)
In this article we address efficiency issues in implementation of Monte Carlo algorithm For 3D capacitance extraction. Error bounds in statistical capacitance estimation are discussed. Methods to tighten them through variance reduction techniques are detailed. Sample values in implementation of Monte Carlo algorithm are completely determined by the first(More)
This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are(More)
Traditionally, automatic design rule correction (DRC) problem is modeled as a Linear Program (LP) with design rules as difference constraints under minimum perturbation objective. This yields Totally Uni-Modular (TUM) constraint matrices thereby guaranteeing integral grid-compliant solutions with LP solvers. However, advanced technology nodes introduce(More)
With the advent of newer technologies, the underlying manufacturing processes are becoming more complicated. This results in substantial variations between mask and actual fabricated geometries of the conductors. These variations in geometries can lead to significant differences in the interconnect capacitances computed using mask and actual geometries. The(More)