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We present a new parallel, adaptable algorithm, which plays Mastermind game, and its FPGA implementation. The proposed algorithm is a cross between Shapiro's, Knuth's, and Kooi's algorithms, has low-computational complexity but still offers competitive game results. The FPGA design part required subtle architectural decisions and trade-off between area,(More)
Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (low-latency) circuits to carry out this operation. We propose a fast circuit topology called Array-Based maximum finder (AB) to determine both(More)
OBJECTIVE Therapeutic drug monitoring (TDM) is a procedure in which the levels of drugs are assayed in various body fluids with the aim of individualizing the dose of critical drugs, such as cyclosporine A. Cyclosporine A assays are performed in blood. METHODS We proposed the use of the Takagi and Sugeno-type "adaptive-network-based fuzzy inference(More)
We describe a novel methodology to exploit the widely used <i>Dynamic Partial Reconfiguration</i> (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a hardware Trojan in an Advanced Encryption Standard (AES) encryption circuit implemented on a FPGA. The DPR is performed by transferring the required partial configuration bitstream file over(More)
Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuck-open/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is defect-aware even at the crosspoint level. Such logic mapping works with a defect map per each manufactured chip. The problem can be(More)
We present schemes to reduce the compilation time of conngurable hardware that solves Boolean Satiss-ability. The SAT solver presented by Zhong in last year's FCCM conference has a large compilation time overhead mainly due to placement and routing of many FPGAs. We attack the problem on 3 fronts. First, we partitioning the SAT solver into instance-speciic(More)
Dynamic Partial Reconfiguration (DPR) of Xilinx FPGAs in cases where there is significant logic difference between subsequent configurations is made possible by Xilinx module-based PR flow. Xilinx supports this flow only for high-end FPGAs and requires paid license, without which Xilinx PlanAhead software disables the related knobs and features. This poster(More)