Seyyed Ahmad Razavi

  • Citations Per Year
Learn More
3D technology is an attractive solution for reducing wirelength in a field programmable gate array (FPGA). However, trough silicon vias (TSV) are limited in number. In this paper, we propose a tilable switch module architecture based on the 3D disjoint switch module for 3D FPGAs. Experimental results over 20 MCNC benchmarks show 62% reduction in the number(More)
SRAM-based FPGAs suffer from soft errors caused by cosmic particles. This paper introduces a new switch box architecture to mitigate soft errors. In this switch box architecture, the number of SRAM bits required for programming the switch boxes is reduced by means of switch reduction with slight impact on routing capability of the switch box. This(More)
In recent years, parameter variations present critical challenges for manufacturability and yield on integrated circuits. In this paper, a new method for improving the timing yield of field programmable gate array (FPGA) devices affected by random and systematic within-die variation is proposed. By selection of an appropriate configuration from a set of(More)
The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of(More)
  • 1