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The paper presents a new memory-addressing scheme for the realization of low power FFT processors. The scheme is based on the minimization of coefficient access and the reduction of switching activity by modifying the butterfly sequence. Therefore, power consumption in the complex multiplier and memory is significantly saved.
With the explosive growth of multimedia services in today's wireless communications, this paper addresses the Quality of Service (QoS) issue focusing on satisfying the throughput requirement for real-time multimedia applications. An Adaptive Transmission Opportunity (AD-TXOP) scheme for a distributed Wireless Local Area Network (WLAN) system based on IEEE… (More)
Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC) architecture is a promising SoC design solution, offering high computational power with lots of flexibilities. However, finding the optimal MPSoC architecture configuration remains an enormous challenge due to its high structural complexity and functional diversity. In this paper, we… (More)
In wireless local area network (WLAN) environment with independent user fading, at least one user is likely to undergo very good channel state at any time, and this is called multiuser diversity. For high system performance, a transmission scheduler at the LLC layer is required to exploit this multiuser diversity by opportunistically selecting a feasible… (More)
IEEE 802.11e wireless LAN standard supports the call admission control (CAC) for the quality of service (QoS) traffic such as video and voice based on the medium time which means the bandwidth allocation normalized by the arrival time interval of corresponding traffic streams. IEEE 802.11e defines the medium time and its argument, MPDU exchange time which… (More)
This work presents a system architecture and effective co-verification methodologies for the IEEE 802.11a Medium Access Control (MAC) layer/Physical (PHY) layer implementation. The architecture modeling includes hardware/software partitioning of a total system based on timing measurements from the C/C++ and Verilog design, and analysis of real-time… (More)