Seung-Tak Ryu

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This paper presents transformer-based self-starting boost converter architecture with low-power maximum power point tracking (MPPT) control for low-voltage thermoelectric generator applications. The minimum working voltage of the proposed boost converter is 40 mV with oscillation through a positive feedback loop formed by a native MOS and transformer. The(More)
A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between stages reconfigure the capacitor connection of the(More)
The capacitor mismatch in a 1.5-b/stage pipelined ADC is background calibrated in the analog domain using a pseudorandom (PN) dithering concept. The reference voltage added/subtracted during the normal operation is used as a dither to PN-modulate the mismatch error so that it can be embedded into the residue and be recovered later by correlating with the(More)
Capacitive touch-screen panels (TSPs) are widely used in recent high-end mobile products on the basis of their high quality of touch features, as well as superior visibility and durability [1-5]. Capacitive TSPs can be classified into selfcapacitance [1,2] or mutual-capacitance [3-5] types, according to the sensing mechanism. Compared with the(More)
This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit(More)
By taking advantage of the merits of the low power consumption and hardware simplicity of SAR ADCs, 2b/cycle conversion structures in SAR ADCs have been actively studied in recent years for enhanced conversion rates and excellent FoM [1-3]. However, many error sources in the 2b/cycle SAR ADCs, such as mismatches between DACs and comparators, and the(More)