Seung Ki Joo

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The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form(More)
Bottom-gated polycrystalline-silicon (poly-Si) thin-film transistors (TFT's) with a planarized copper (Cu) gate for large-area displays have been fabricated and characterized. The 500 nm depth of trenchs are filled up with 400 nm, 500 nm, 600 nm thickness of Cu using the damascene process of VLSI technology, poly-Si TFT's with 100 nm thick gate insulator(More)
In this study, we studied the effect of the electrical stress on the on-current of metal-induced laterally crystallized poly-Si TFTs. It was found that the electrical performance of polycrystalline silicon thin-film transistors (TFTs) is greatly affected by the electrical stress. Under the electrical stress condition, the drain current increases due to(More)
Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3(More)
In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix(More)
A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT(More)
References 1. Park, J.-H. & Joo, S.-K. Quasi-Single-Grain Pb(Zr,Ti)O3 on Poly-Si TFT for Highly Reliable Nonvolatile Memory Device. IEEE Transactions on Device and Materials Reliability 15, 417–422, doi: 10.1109/TDMR.2015.2455506 (2015). 2. Park, J.-H. & Joo, S.-K. A Novel Metal-Ferroelectric-Insulator-Silicon FET With Selectively Nucleated Lateral(More)
It has been known that LDD is essential to reduce the leakage current in poly TFTs, which has been regarded as one of the most important issues in poly TFT characteristics. However, according to the conventional process, an extra mask is needed solely for the LDD formation, which is not only complicated but also difficult to maintain the reproducibility. In(More)
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