• Publications
  • Influence
A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC
  • M. Kim, G. Ahn, +6 authors U. Moon
  • Engineering, Computer Science
  • IEEE Journal of Solid-State Circuits
  • 22 April 2008
TLDR
A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. Expand
  • 63
  • 2
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A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control
  • M. Choi, Sung-No Lee, +4 authors H. Lee
  • Physics, Computer Science
  • IEEE Custom Integrated Circuits Conference
  • 17 November 2008
TLDR
A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm2. Expand
  • 26
  • 1
A 0.9V 92dB Double-Sampled Switched-RC SD Audio ADC
  • M. Kim, G. Ahn, +6 authors U. Moon
  • Computer Science
  • Symposium on VLSI Circuits, . Digest of Technical…
  • 15 June 2006
TLDR
A 0.9V third-order 1.5bit delta-sigma ADC with simple dynamic element matching (DEM) is presented with 92dB DR, 91dB SNR and 89dB SNDR. Expand
  • 13
  • 1
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A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure
TLDR
A 2.7V 4mW per-channel 20-bit 48kS/s sigma-delta stereo audio DAC, integrated in a 0.13mum CMOS technology, achieves a dynamic range (DR) of 101dB and occupies an active die area of 0.82mm2. Expand
  • 7
  • 1
A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer
TLDR
A switched-capacitor second-order audio ΔΣ analog-to-digital converter (ADC) is presented with low-distortion input feed-forward architecture to relax the linearity requirement of the integrators. Expand
  • 5
A 1.3-mW per-channel 103-dB SNR stereo audio DAC with class-D head-phones amplifier in 65nm CMOS
TLDR
The stereo audio DAC with novel single-ended class-D amplifier achieving a 103-dB SNR is fully integrated in a 65 nm CMOS technology. Expand
  • 6
A calibration-free 3V 16b 500kS/s 6mW 0.5mm/sup 2/ ADC with 0.13 /spl mu/m CMOS
TLDR
A calibration-free 3V 6mW 16-bit 500kS/s cyclic ADC with an active die area of 0.5mm/sup 2/ is implemented in a 0.13 /spl mu/m CMOS. Expand
  • 5
A 3.3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter
TLDR
A calibration-free 3.3 V 14-bit 10 MSPS pipelined analog-to-digital (A/D) converter was implemented using a 0.35 /spl mu/m CMOS technology. Expand
  • 5
A 10-bit, 40 Msamples/s cascading folding and interpolating A/D converter with wide range error correction
This paper describes a 10-bit, 10-Msamples/s CMOS folding and interpolating analog-to-digital converter (F&I ADC). A new cascading architecture is proposed to reduce the number of comparators andExpand
  • 5
A 100-dB gain-corrected delta-sigma audio DAC with headphone driver
TLDR
An oversampled digital-to-analog converter with a 100-dB A-weighted dynamic range is presented. Expand
  • 1
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