SIFT is a widely-used algorithm that extracts features from images; using it to extract information from hundreds of terabytes of aerial and satellite photographs requires paral-lelization in order to be feasible. We explore accelerating an existing serial SIFT implementation with OpenMP parallelization and GPU execution.
The paper presents the new hardware thread interface (HWTI), a meaningful and semantic rich target for a high level language to hardware descriptive language translator. The HWTI provides a hardware thread with the same thread system calls available to software threads, a fast global distributed memory, support for pointers, a generalized function call… (More)
Given multiple images of the same scene, image registration is the process of determining the correct transformation to bring the images into a common coordinate system—i.e., how the images fit together. Feature-based registration applies a transformation function to the input images before performing the correlation step. The result of that transformation,… (More)
We describe an approach to parallelizing SIFT and other scale-space-based feature transformation algorithms. By partitioning the workload in a novel fashion, our approach can take advantage of all forms of parallelism: the shared-memory parallelism of threaded programming, the distributed-memory approach of cluster programming, and GPU-based acceleration.… (More)
Thanks to advancements in fabrication techniques, it will soon be possible to place 10's if not 100's of cores on a single hybrid CPU/FPGA reconfigurable chip. This has lead to a new field of study, namely Multi-Core Systems on a Programmable Chip (MCSoPC). The problems being studied with MCSoPC are not unlike the problems studied 20 years ago when multiple… (More)