Seshasayanan Ramachandran

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Technological growth in semiconductor industry have led to unprecedented demand for faster, area efficient and low power VLSI circuits for complex image processing applications. DWT-IDWT is one of the most popular IP that is used for image transformation. In this work, a high speed, low power DWT/IDWT architecture is designed and implemented on ASIC using(More)
Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to(More)
Image compression demands high speed architectures for transformation and encoding process. Medical image compression demands lossless compression schemes and faster architectures. A trade-off between speed and area decides the complexity of image compression algorithms. In this work, a high speed DWT architecture and pipelined SPIHT architecture is(More)
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