Seshasayanan Ramachandran

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Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to(More)
This paper presents the design and characterization of a completely pipelined Null Convention Logic based IEEE 32 bit single precision floating point multiplier using full word and bit wise completion strategies. Performance metrics such as speed, area and power of the Null convention logic pipelined floating point multiplier, obtained from Xilinx(More)
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