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In this paper a channelizer implementation is performed on FPGA by first a demonstration through simulation and then by applying real test signals. In this study, polyphase FFT based method is selected as the channelization method. The wideband signal, with the bandwidth of 50 MHz, is sampled by 105 MHz and divided into 64 channels with the channel spacing… (More)
In this work, a hierarchical algorithm and a hardware architecture for bi-dimensional fast empirical mode decomposition (B-EMD) is proposed. Using the proposed low cost architecture, decomposing images, video and hyper spectral images using the power of dedicated hardware will be possible.