Sergio Bampi

Learn More
Abstract: This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression. This architecture is used as the core of a JPEG compressor and is the critical path in JPEG compression hardware. The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole(More)
We present a new architecture for signed multiplication. The proposed architecture maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. We propose a Hybrid encoding for the architectures, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching(More)
This work proposes a hardware architecture for the Intra Frame Prediction of the emerging High Efficiency Video Coding (HEVC) standard. The architecture was designed considering all innovative features of the Intra Prediction included in the HEVC, i.e. all modes and all Prediction Units (PU) sizes. Performance and memory accesses are a problem in the HEVC(More)
The JPEG2000 standard defines the discrete wavelet transform (DWT) as a linear space-to-frequency transform of the image domain in an irreversible compression. This irreversible discrete wavelet transform is implemented by FIR filter using 9/7 Daubechies coefficients or a lifting scheme of factorizated coefficients from 9/7 Daubechies coefficients. This(More)
This paper presents the design of a JPEG compressor for color images targeting high performance in a low cost FPGA device. The JPEG compressor architecture achieves high throughput with a deep and optimized pipeline and with a multiplierless datapath architecture. The architecture was synthesized to Altera FPGAs and the synthesis results and relevant(More)
This work presents a method to design parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation with reduced number of adders and logic depth in the multiplier block. The proposed method uses a combination of two approaches: first, the reduction of the coefficients to N-Power-of-Two (NPT) terms, where N is the(More)