We propose a new efficient automatic verification technique, Athena, for security protocol analysis. It uses a new efficient representation — our extension to the Strand Space Model, and utilizes techniques from both model checking and theorem proving approaches. Athena is fully automatic and is able to prove the correctness of many security protocols with… (More)
Most verification approaches assume a mathematical formalism in which functions are total, even though partial functions occur naturally in many applications. Furthermore , although there have been various proposals for logics of partial functions, there is no consensus on which is " the right " logic to use for verification applications. In this paper, we… (More)
This is our abstract. And this is the Brayton's paper reference: 18].
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algorithm  for out-of-order instruction scheduling. Our approach is similar to the idea of uninterpreted function symbols . We use symbolic values and instructions instead of concrete… (More)
We present a new way of using Binary Decision Diagrams in automata based algorithms for solving the satisfiability problem of quantifier-free Pres-burger arithmetic. Unlike in previous approaches [5, 2, 19], we translate the satis-fiability problem into a model checking problem and use the existing BDD-based model checker SMV  as our primary engine. We… (More)
Efficient decision procedures for arithmetic play a very important role in formal verification. In practical examples, however, arithmetic constraints are often mixed with constraints from other theories like the theory of arrays, Boolean satisfiability (SAT), bit-vectors, etc. Therefore, decision procedures for arithmetic are especially useful in… (More)
A rst-order modal-calculus is introduced as a convenient logic for reasoning about processes with value passing. For this logic we present a proof system for model checking sequential processes deened in the value passing CCS. Soundness of the proof system is established. The use of the system is demonstrated on two small but instructive examples.
We present a new technique for verification of complex hardware devices that allows both generality and a high degree of automation. The technique is based on our new way of constructing a " lightweight " completion function together with new encoding of uninterpreted functions called reference file representation. Our technique combines our completion… (More)