Sergei Devadze

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A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient(More)
Many contemporary electronic systems are based on System-on-Chips (SoC) such as micro-controllers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Boundary Scan(More)
In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the(More)
The main purpose of this paper is to refine the benefits of the FPGA-based synthetic instrumentation concept (see Section 1) proposed by us earlier [1] as well as to provide some new experimental data based on real industrial designs to show the efficiency of our methodology (see Section 2). I. FPGA-BASED EMBEDDED SYNTHETIC INSTRUMENTS The usage of FPGAs in(More)