Sergei Devadze

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Many contemporary electronic systems are based on System-on-Chips (SoC) such as micro-controllers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Boundary Scan(More)
A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient(More)
In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the(More)
A new method based on the critical path tracing is proposed for fault simulation in combinational parts of digital systems. The novelty of the method lays in the possibility to carry out complex computations on sets of faults in parallel simultaneously for many test patterns. A topological analysis is carried out to generate an efficient optimized model for(More)