Serge Maginot

Learn More
once-off basis in order to combine their two models on a chip. A typical model consists of a large number of hierarchical entity-architecture pairs that interface with a set of packages. These packages may be used for describing the environment surrounding the model such as a library of units representing the underlying technology or some common functions,(More)
This paper looks at the design of one successful hardware description language, VHSIC Hardware Description Language (VHDL) with a critical evaluation of particular language features. In the paper we identify features of VHDL that burden the language in terms of development time (i.e. price), performance of the implementation, and user-friendliness. We(More)
In this paper we show that by performing some VHDL elaboration transformations before synthesis we can extend the synthesis subset to include complex structural and hierarchical statements. This in turn means that: • Design, debug and simulation times are reduced • Designs are more accessible (readable, modifiable, portable, reusable) • Design prototyping(More)
In this paper, we present a methodology whereby the whole synthesis and prototyping cycle can be speeded up simply by extending the acceptable VHDL subset to include hitherto unsynthesisable constructs. VHDL elaboration transformations as well as some compiler optimisation techniques can be performed to ensure that the VHDL model is still acceptable by(More)
  • 1