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This paper looks at the design of one successful hardware description language, VHSIC Hardware Description Language (VHDL) with a critical evaluation of particular language features. In the paper we identify features of VHDL that burden the language in terms of development time (i.e. price), performance of the implementation, and user-friendliness. We(More)
In this paper we show that by performing some VHDL elaboration transformations before synthesis we can extend the synthesis subset to include complex structural and hierarchical statements. This in turn means that: • Design, debug and simulation times are reduced • Designs are more accessible (readable, modifiable, portable, reusable) • Design prototyping(More)
Tagant: VHDL language extensions to support abstraction and re-use. sages—in the object-oriented meaning— dynamically to the receiver objects which are able to process that message. 7.5 Message passing The invocation of a method (subprogram) of a type object has the semantics of a procedure call. Methods of a special object can be invoked by a qualified(More)
In this paper, we present a methodology whereby the whole synthesis and prototyping cycle can be speeded up simply by extending the acceptable VHDL subset to include hitherto unsynthesisable constructs. VHDL elaboration transformations as well as some compiler optimisation techniques can be performed to ensure that the VHDL model is still acceptable by(More)
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