- Full text PDF available (4)
- This year (0)
- Last five years (0)
once-off basis in order to combine their two models on a chip. A typical model consists of a large number of hierarchical entity-architecture pairs that interface with a set of packages. These packages may be used for describing the environment surrounding the model such as a library of units representing the underlying technology or some common functions,… (More)
This paper looks at the design of one successful hardware description language, VHSIC Hardware Description Language (VHDL) with a critical evaluation of particular language features. In the paper we identify features of VHDL that burden the language in terms of development time (i.e. price), performance of the implementation, and user-friendliness. We… (More)
VHDL is compared to three other well-known hardware description languages : Verilog (from Cadence Design Systems, now public), UDLII (new Japanese standard) and M from Mentor Graphics). This comparative study parallels the fundamental concepts of these languages and highlights the different design processes and methodologies they reqw " re.
In this paper we show that by performing some VHDL elaboration transformations before synthesis we can extend the synthesis subset to include complex structural and hierarchical statements. This in turn means that: • Design, debug and simulation times are reduced • Designs are more accessible (readable, modifiable, portable, reusable) • Design prototyping… (More)
Tagant: VHDL language extensions to support abstraction and re-use. sages—in the object-oriented meaning— dynamically to the receiver objects which are able to process that message. 7.5 Message passing The invocation of a method (subprogram) of a type object has the semantics of a procedure call. Methods of a special object can be invoked by a qualified… (More)