Seonpil Kim

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— Increasing number of processor cores on a chip is a driving force to move to three-dimensional integration. On the other hand, as the number of processor cores increases, non-uniform cache architecture (NUCA) receives growing attention. Reducing effective memory access time, including cache hit time and miss penalty, is crucial in such multi-processor(More)
— Dynamic voltage scaling (DVS) is a very powerful technique in reducing dynamic power consumption of CMOS circuits. Recent studies showed that intra-task DVS method which adjusts the voltage level during program execution can achieve significant energy reduction. However, the overhead of large number of voltage switching becomes a limitation for its(More)
— In H.264/AVC decoder system, motion compensator (MC) is the most critical component in terms of computational complexity and memory access. We propose Data Reuse method between Heterogeneous Partitions (DRHP) to reduce the memory access of MC. Our method reuses data in the overlapped region between memory access regions of neighboring blocks in the(More)
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