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— Increasing number of processor cores on a chip is a driving force to move to three-dimensional integration. On the other hand, as the number of processor cores increases, non-uniform cache architecture (NUCA) receives growing attention. Reducing effective memory access time, including cache hit time and miss penalty, is crucial in such multi-processor(More)
— Dynamic voltage scaling (DVS) is a very powerful technique in reducing dynamic power consumption of CMOS circuits. Recent studies showed that intra-task DVS method which adjusts the voltage level during program execution can achieve significant energy reduction. However, the overhead of large number of voltage switching becomes a limitation for its(More)
– It is important in SoC design that the design and verification can be done easily and quickly. And RT-level simulation in verification methods is still necessary, but the usage is limited by its slow speed. Therefore we propose a SoC verification environment in which hardware parts are accelerated in FPGA and cores are modeled with ISS. To connect ISS in(More)
— The biggest problem with SoC design is that there are two distinct heterogeneous development environments for hardware and software; Software engineers use software development tools such as compilers and debuggers to develop software codes for processor cores. Hardware engineers use traditional HDL development tools such as logic synthesizer and HDL(More)
— In H.264/AVC decoder system, motion compensator (MC) is the most critical component in terms of computational complexity and memory access. We propose Data Reuse method between Heterogeneous Partitions (DRHP) to reduce the memory access of MC. Our method reuses data in the overlapped region between memory access regions of neighboring blocks in the(More)
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