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Advanced CMOS technologies are highly susceptible to process, voltage, and temperature (PVT) variations due to sub-wavelength lithography and other manufacturing challenges. These variations cause performance uncertainty for which timing margins must be added to guarantee correct operation. Ultimately, this results in lost performance or energy: performance(More)
In-situ error-detection and correction techniques have a strong potential to eliminate the worst-case margins in ultra-low-voltage (ULV) pipelines while achieving high variation tolerance. Adding the capability of error detection, however, can incur large hardware overhead, especially in ULV due to the larger variability. In this paper, we analyze the(More)
—Embedded scalable platforms (ESP) are a novel generation of platform architectures that yield optimal energy-performance operations while supporting a diversity of embedded application workloads. A companion methodology combines full-system simulation, pre-designed HW/SW interface libraries, high-level synthesis and FPGA prototyping to enable an effective(More)