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Advanced CMOS technologies are highly susceptible to process, voltage, and temperature (PVT) variations due to sub-wavelength lithography and other manufacturing challenges. These variations cause performance uncertainty for which timing margins must be added to guarantee correct operation. Ultimately, this results in lost performance or energy: performance(More)
In-situ error-detection and correction techniques have a strong potential to eliminate the worst-case margins in ultra-low-voltage (ULV) pipelines while achieving high variation tolerance. Adding the capability of error detection, however, can incur large hardware overhead, especially in ULV due to the larger variability. In this paper, we analyze the(More)
Ultra-dynamic-voltage-scaling (UDVS) is a compelling technique to use nominal supply voltage (V<sub>DD</sub>) for providing peak performance while achieving high energy efficiency by opportunistically using near/sub-threshold VDDs under average and low workload. One of the challenges in developing UDVS systems is that circuit fabrics optimized for a(More)
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