Seonggun Kim

Learn More
Mobile users frequently want mobile devices as powerful as desk top PCs, but still in a small and light form factor. The level of users' demand is yet too high to satisfy with current technology. Available resources such as CPU, memory, and battery power are still insufficient for current mobile devices. One way to overcome these limitations is to offload(More)
Multicore architectures are evolving with the promise of extreme performance for the classes of applications that require high performance and large bandwidth of memory. Irregular reduction is one of important computation patterns for many complex scientific applications, and it typically requires high performance and large bandwidth of memory. In this(More)
In imperative synchronous languages, a statement is called schizophrenic if it is executed more than once in a single clock. When a schizophrenic statement is translated into a circuit, the circuit can behave abnormally because of the multiple executions. To solve the problems caused by schizophrenic statements, compilers duplicate the statements to avoid(More)
Mobile consumer devices take increasingly important roles, more closely and personally interacting with users. As users get used to mobile devices, they often want the same level of computing experience as they can have from desktop PCs, but still in small and light form factors. Considering current technology, we find the limitations of the processor and(More)
In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remapping scheme for dynamically allocated structures in order to provide better locality than conventional field layouts. Our proposed scheme reduces cache miss rates drastically by(More)
Many researches aim to improve memory management for performance, efficiency, ease of use, and safety. Region-based memory management, a newly investigated technique for memory-limited mobile devices, splits the heap into one global (persistent) region, and multiple local regions – one local region per method invocation. Each object allocation is initially(More)
Aggressive embedded processors are often equipped with general purpose cores and special purpose acceleration logics. In our paper, we consider a reconfigurable processor that consists of very long instruction word (VLIW) cores and coarse grained reconfigurable arrays (CGRAs). CGRAs are particularly used to enhance the performance by exploiting loop(More)
Recent electronic devices are equipped with processors extended with multicore accelerators to take advantage of the powerful performance from acceleration co-processors. Applications on such high-end electronic products require capability to run graphic-rich applications. Scalable acceleration co-processors are frequently designed as multicores with(More)
  • 1