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A DLL(Delay Locked Loop) with DCC(Duty Cycle Correction) has become an essential block in high speed memory and digital circuits. An SMD(Synchronous Mirror Delay) structure is widely used both for skew reduction and for DCC. In this paper, an area-efficient DLL structure based on the merged dual SMD is proposed. The merged structure allows the forward delay(More)
This paper presents the design of a clock and data recovery circuit (CDR) without a reference clock. It has a phase and frequency detector (PD and FD), which incorporates a half-rate bang-bang type oversampling PD and a half-rate digital quadricorrelator frequency detector (DQFD) that can achieve low-jitter operation and improve pull-in range. It also has a(More)
This paper proposes an architecture of 3 rd order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce power consumption and area. The proposed SDM improve the architecture of conventional 3 rd order SDM which consists of two integrators. In the proposed architecture, the coefficient values of the first stage are doubled by inserting(More)
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