Seon-Ho Han

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A single chip rendering engine that consist of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32b RISC core is proposed for the low power 3D-graphics in portable system. The 56mm2 prototype integrating edge processor, 8 pixel processors, 8 frame buffers and RISC core is fabricated using 0.35um CMOS Embedded Memory Logic(More)
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