Seon-Ho Han

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—A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three(More)
A single chip rendering engine that consist of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32b RISC core is proposed for the low power 3D-graphics in portable system. The 56mm2 prototype integrating edge processor, 8 pixel processors, 8 frame buffers and RISC core is fabricated using 0.35um CMOS Embedded Memory Logic(More)
A fully integrated receiver front-end, reconfigured by a frequency locking scheme using a PLL, is implemented in a 0.18 /spl mu/m triple-well CMOS technology. The receiver front-end is composed of a discretely tunable low noise amplifier (DT-LNA), a quadrature down mixer, and a discretely and continuously tunable frequency synthesizer (DCT-FS) with an(More)
A CMOS Variable Gain Amplifier (VGA) is proposed for high frequency and low power broadband communication systems, such as Ultra-Wide Band (UWB) receiver. The VGA consists of a P/NMOS complimentary differential-pair with source degeneration, a high-swing current mirror stage with capacitive feedforward frequency compensation, and resistive load. Description(More)
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