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—Current processor designs have a critical operating point that sets a hard limit on voltage scaling. Any scaling beyond the critical voltage results in exceeding the maximum allowable error rate, i.e., there are more timing errors than can be effectively and gainfully detected or corrected by an error-tolerance mechanism. This limits the effectiveness of(More)
Approximation can increase performance or reduce power consumption with a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic can be used to generate sufficient results rather than absolutely accurate results. Approximate design exploits a tradeoff(More)
Process and device scaling in late-CMOS technologies highlight leakage power as a critical challenge for the semiconductor industry. Careful gate sizing and <i>V</i><sub><i>th</i></sub>-swapping can reduce leakage, but prior optimizations based on convex or dynamic programming (<i>i</i>) are often based on unrealistic assumptions about circuit delay and(More)
Modern digital IC designs have a <i>critical operating point</i>, or "wall of slack", that limits voltage scaling. Even with an error-tolerance mechanism, scaling voltage below a critical voltage - so-called <i>overscaling</i> - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage scaling in(More)
Conventional CAD methodologies optimize a processor module for correct operation, and prohibit timing violations during nominal operation. In this paper, we propose <i>recovery-driven design</i>, a design approach that optimizes a processor module for a target timing error rate instead of correct operation. We show that significant power benefits are(More)
The well-studied gate-sizing optimization is a major contributor to IC power-performance tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of constraints, scale to large circuits, and effectively utilize a large (but finite) number of possible gate configurations, including <i>V</i><sub><i>t</i></sub> and(More)
We propose a low-overhead technique, Token-Based Adaptive Power Gating (TAP), to power gate an actively executing out-of-order core during memory accesses. TAP tracks every system memory request, providing a lower-bound estimate for the response time. TAP also tracks the state of every power-gateable core in the system, to provide minimal latency wake-up(More)
— The proliferation of embedded systems and mobile devices has created an increasing demand for low-energy hardware. Dynamic voltage and frequency scaling (DVFS) is a popular energy reduction technique that allows a hardware design to reduce average power consumption while still enabling the design to meet a high-performance target when necessary. To(More)
—Conventional computer-aided design (CAD) methodologies optimize a processor module for correct operation and prohibit timing violations during nominal operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate (ER) instead of correct operation. The target ER is chosen based on how many(More)
In mobile systems, the problems of short battery life and increased temperature are exacerbated by wasted leakage power. Leakage power waste can be reduced by power-gating a core while it is stalled waiting for a resource. In this work, we propose and model <i>memory access power gating</i> (MAPG), a low-overhead technique to enable power gating of an(More)