Seokhyeong Kang

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Approximation can increase performance or reduce power consumption with a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic can be used to generate sufficient results rather than absolutely accurate results. Approximate design exploits a tradeoff(More)
Modern digital IC designs have a <i>critical operating point</i>, or "wall of slack", that limits voltage scaling. Even with an error-tolerance mechanism, scaling voltage below a critical voltage - so-called <i>overscaling</i> - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage scaling in(More)
Current processor designs have a critical operating point that sets a hard limit on voltage scaling. Any scaling beyond the critical voltage results in exceeding the maximum allowable error rate, i.e., there are more timing errors than can be effectively and gainfully detected or corrected by an error-tolerance mechanism. This limits the effectiveness of(More)
The well-studied gate-sizing optimization is a major contributor to IC power-performance tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of constraints, scale to large circuits, and effectively utilize a large (but finite) number of possible gate configurations, including <i>V</i><sub><i>t</i></sub> and(More)
Process and device scaling in late-CMOS technologies highlight leakage power as a critical challenge for the semiconductor industry. Careful gate sizing and <i>V</i><sub><i>th</i></sub>-swapping can reduce leakage, but prior optimizations based on convex or dynamic programming (<i>i</i>) are often based on unrealistic assumptions about circuit delay and(More)
Aggressive requirements for low power and high performance in VLSI designs have led to increased interest in approximate computation. Approximate hardware modules can achieve improved energy efficiency compared to accurate hardware modules. While a number of previous works have proposed hardware modules for approximate arithmetic, these works focus on(More)
The proliferation of embedded systems and mobile devices has created an increasing demand for low-energy hardware. Dynamic voltage and frequency scaling (DVFS) is a popular energy reduction technique that allows a hardware design to reduce average power consumption while still enabling the design to meet a high-performance target when necessary. To conserve(More)
Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to (ii) improve design performance (e.g., timing speculation). However, significant overheads (e.g., 16&percnt; and 14&percnt; energy penalties due to throughput degradation and additional circuits) are incurred by existing resilient design techniques. For(More)
Conventional CAD methodologies optimize a processor module for correct operation, and prohibit timing violations during nominal operation. In this paper, we propose <i>recovery-driven design</i>, a design approach that optimizes a processor module for a target timing error rate instead of correct operation. We show that significant power benefits are(More)