Sek M. Chai

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—On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process. This paper presents a set of heterogeneous architectural models that combines architecture description and Rent's Rule-based wiring models. These architecture models allow flexible heterogeneous system(More)
Gigascale Integration (GSI) enables a new generation of monolithic focal plane processing systems built with billion-transistor chips. As this technology matures, fundamental technology limitations on wire interconnects and power dissipation will become the performance bottleneck. This paper presents system performance projections for GSI technologies under(More)
Smart pixel architectures offer important new opportunities for low cost, portable image processing systems. They provide greater I/O bandwidth and computing performance than systems based on CCD and microprocessors. However, finding a balance between performance, flexibility, efficiency, and cost depends on an evaluation of target applications. This paper(More)
ÐPortable image processing applications require an efficient, scalable platform with localized computing regions. This paper presents a new class of area I/O systolic architecture to exploit the physical data locality of planar data streams by processing data where it falls. A synthesis technique using dependence graphs, data partitioning, and computation(More)
High performance portable and space-borne systems continue to demand increasing computation speeds while concurrently attempting to satisfy size, weight, and power constraints. As multipro-cessor systems become necessary to satisfy the computational requirements, interconnection network design will become subject to similar constraints. This paper focuses(More)
Future military scenarios will rely on advanced imaging sensor technology beyond the visible spectrum to gain total battlefield awareness. Real-time processing of these data streams requires tremendous computational workloads and I/O throughputs. This paper presents three applications for hyper-spectral data streams, vector quantization, region autofocus,(More)
This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE(More)