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This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE(More)
On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process. This paper presents a set of heterogeneous architectural models that combines architecture description and Rent’s Rule-based wiring models. These architecture models allow flexible heterogeneous system(More)
Smart pixel architectures offer important new opportunities for low cost, portable image processing systems. They provide greater I/O bandwidth and computing performance than systems based on CCD and microprocessors. However, finding a balance between performance, flexibility, efficiency, and cost depends on an evaluation of target applications. This paper(More)
ÐPortable image processing applications require an efficient, scalable platform with localized computing regions. This paper presents a new class of area I/O systolic architecture to exploit the physical data locality of planar data streams by processing data where it falls. A synthesis technique using dependence graphs, data partitioning, and computation(More)
Gigascale Integration (GSI) enables a new generation of monolithic focal plane processing systems built with billion-transistor chips. As this technology matures, fundamental technology limitations on wire interconnects and power dissipation will become the performance bottleneck. This paper presents system performance projections for GSI technologies under(More)
The memory subsystem for computer vision and image processing applications must sustain high memory bandwidth to keep processors busy. This paper advocates the use of stream descriptors, a mechanism that allows programmers to indicate data movement explicitly. Stream descriptors enable the compiler to organize memory transfers more efficiently by matching(More)
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based system on chip (SoC) that meet the applications requirements. The designer can customize the hardware by selecting from a large number of pre-defined peripherals and fixed IP functions and by providing new hardware, typically expressed using RTL. Hardware(More)
Real-time image processing requires high computational and I/O throughputs obtained by use of optoelectronic system solutions. A novel architecture that uses focal-plane optoelectronic-area I/O with a fine-grain, low-memory, single-instruction-multiple-data (SIMD) processor array is presented as an efficient computational solution for real-time(More)
Fisheye lenses are often used in scientific or virtual reality applications to enlarge the field of view of a conventional camera. Fisheye lens distortion correction is an image processing application which transforms the distorted fisheye images back to the natural-looking perspective space. This application is characterized by non-linear streaming memory(More)