Seiyang Yang

Learn More
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feedback cycles are reduced with minimal switching activity on the state variables. Experiment shows significant improvement in power dissipation and testabilities for benchmark(More)
Multilevel temporal-parallel event-driven simulation is a new radically different approach to simulation of designs described in Verilog HDL. It is based on a concept of time-parallel simulation applied to gate-level timing simulation. The simulation is performed in two steps: 1) fast reference simulation that runs on a higher, reference-level design model(More)
This paper describes a new and efficient solution to a distributed event-driven gate-level HDL simulation. It is based on a novel concept of spatial parallelism using accurate prediction of input and output signals of individual local modules in local simulations, derived from a model at a higher abstraction level (RTL). Using the predicted rather than(More)
Simulation speedup offered by distributed parallel event-driven simulation is known to be seriously limited by the synchronization and communication overhead. These limiting factors are particularly severe in gate-level timing simulation. This paper describes a radically different approach to gate-level simulation based on a concept of temporal rather than(More)
Multi-core processors have become common in current computing platforms. Today, most of multi-core workstations and PCs have adopted NUMA (Non-Uniform Memory Access) advanced memory architecture for high performance and scalability. In response, EDA (Electronic Design Automation) community has applied significant effort to parallelize many EDA algorithms(More)
This paper introduces a radically different approach to parallel simulation for gate level design, aimed at completely eliminating the communication and synchronization overhead between simulators. It is based on a new concept of temporal parallel simulation: in contrast to traditional, spatiallydistributed simulation, which partitions the design into(More)
This paper addresses the problem of computing relationship between the states of two designs, specification and implementation. The problem is considered here in the context of temporal parallel simulation, where state matching is required to determine the initial values of registers used as starting points for individual simulation runs. This problem is(More)