Seiji Inumiya

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Gate stacks consisting of a sub-1nm equivalent oxide thickness (EOT) high-k gate dielectric and a metal gate electrode are required for low operation power (LOP) devices in the hp45 node and beyond (1). Although it is difficult to reduce the EOT of a gate stack without degrading mobility, it has recently been demonstrated that this difficulty could be(More)
1. Introduction HfSiON is considered the most promising candidate of gate dielectrics for hp65 node LSTP devices due to its high mobility [1-2]. Sub-1nm EOT high-k gate dielectrics are required for LOP devices in hp45 node and beyond [3]. However, the k-value of HfSiON is 16 at most. In order to obtain sub-1nm EOT, the physical thickness of HfSiON must be(More)
In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k gate dielectrics, thin body SOI, and multi-gate transistor, are proposed so far. Among these technologies, gate stack technology(More)
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