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We have realized a 0.9nm-EOT TaSix/HfSiON gate stack that exhibits the high electron mobility of 264 cm 2 /Vs @ 0.8MV/cm (86% of thermal SiO 2), even after spike annealing at 1000ºC. This was achieved by using thermally-stable HfSiON gate dielectrics with plasma nitridation, in which interfacial layer growth due to recoiled oxygen had been successfully(More)
In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k gate dielectrics, thin body SOI, and multi-gate transistor, are proposed so far. Among these technologies, gate stack technology(More)
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