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Journals and Conferences
The operation of 1–3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mode (for either front or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, large influence of substrate depletion underneath the buried oxide, absence of drain current transients, degradation in electron mobility are… (More)
This paper describes the Velotrace, a mechanical device designed to allow the collection of analog data on velar position. The device consists of two levers connected through a push rod and carried on a pair of thin supports rods. The device is positioned in the nasal passage with the internal lever resting on the nasal surface of the velum and the external… (More)
This paper describes, from the viewpoint of device fabrication, single-electron and quantum devices using silicon-oninsulators (SOIs). We point out that control of the oxidation of Si is quite important and could be the key to their fabrication. We also introduce our technique for making single-electron transistors (SETs), which uses special phenomena that… (More)
This paper describes an approach to reducing short-channel effects in small-dimension MOSFET's, with emphasis focused on the geometrical channel structure along a gate. To minimize threshold-voltage sensitivities, the advantage of an inhomogeneous channel structure with a highly doped region near the source is demonstrated through a theoretical analysis and… (More)
An accurate three-dimensional analysis of semiconductor devices based on the general transport equations is carried out. In this analysis, the finite difference formulation and ICCG (Incomplete Choleski and Conjugate Gradient) methods are utilized to reduce computational time and memory requirements. The algorithms are applied to a wide variety of devices,… (More)
The systematic application of two-dimensional analysis for the bipolar device design is described. In this analysis, surface recombination is taken into account by properly modifying the carrier lifetime term, in addition to mobility variations and bandgap narrowing effects. Moreover, an effective method to obtain terminal currents from the calculated… (More)
A fully ECL compatible bipolar master slice LSI with a loaded gate delay of 500ps and power dissipation of less than 6W will be reported. A 1.5μm design rule bipolar process employing three levels of metalization has been utilized.
To improve performance compared with a previously developed 5K-gate gate array, advanced process technology is used. A 47% smaller emitter window opening technique is used which results in an approximately 0.7-/spl mu/m-wide emitter. Furthermore, the speed-up capacitance of the basic nonthreshold logic cell is increased by 33% over that of the earlier gate… (More)
An integrated method which combines modular and standard -cell techniques with automated PLA design to implement a 16b microcomputer will be reported. A CAD system was used to achieve less than 20 man-month design time.
A 32b CMOS VLSI processor chip designed automatically, including 17K gates of random logic and 2304b RAM will be described. Silicon gate technology offers an average loaded propagation delay of 1.6ns/gate using 2μm design rules.