Sei Seung Yoon

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Random variations play a critical role in determining SRAM yield, by affecting both the bitcell and the read sense amplifiers (SA). In this work, a process control monitor for SRAM SA offset is proposed and implemented in 28nm LP CMOS technology. The monitor provides accurate measurement of SA offset from a large sample size and accounts for all proximity(More)
The increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. This is aggravated by the strong demand for lower cost and power consumption, higher performance and density which complicates SRAM design process. In this paper, we present a methodology for statistical simulation of SRAM read(More)
Embedded SRAM dominates modern SoCs, and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, the large increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. In the presence of large process variations, SRAMs are(More)
Models for cache yield and coverage for radiation-induced soft errors quantify the trade-off between the minimum supply voltage (V<sub>MIN</sub>) and the soft-error protection when applying error-correcting codes (ECC) to a cache. Model predictions of the V<sub>MIN</sub> benefit and soft-error coverage agree closely with silicon measurements from a 7Mb data(More)
Mobile devices spend most of the time in standby mode. Supported features and functionalities are increasing in each newer model. With the wide spread adaptation of multi-tasking in mobile devices, retaining current status and data for all active tasks is critical for user satisfaction. Extending battery life in portable mobile devices necessitates the use(More)
Invited Abstract Keith Bowman, Alex Parkt, Venkat Narayanant, Francois Atallah, Alain Artierit, Sei Seung Yoont, Kendrick Yuent, and David Hansquine Qualcomm, Raleigh, NC tQualcomm, San Diego, CA Circuit techniques for reducing the minimum supply voltage (V MiN) of last-level and intermediate static random-access memory (SRAM) caches enhance processor(More)
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