Sebastian Meisner

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With ever-decreasing CMOS transistor sizes, integrated circuits are becoming more and more susceptible to errors. A commonly used approach to improve the reliability of digital circuits is triple modular redundancy (TMR). TMR instantiates three copies of a circuit plus additional voter circuits to take majority decisions on the output values. Prior research(More)
The reliability of FPGA based hardware designs is becoming a challenge with future device technologies and, in particular, for avionic and space applications where FPGAs might get exposed to high radiation levels. Typically, redundancy-based techniques are used to achieve fault-tolerant operation. However, hardware redundancy comes with an overhead in(More)
In this paper we present how Intel's Single-Chip-Cloud processor behaves for parallel macro pipeline applications. Subsets of the SCC's available cores can be arranged as a pipeline where each core processes one stage of the overall workload. Each of the independent cores processes a small part of a larger task and feeds the following core with new data(More)
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