Sebastian Hessel

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In this paper we present detailed profiling results and identify the time critical algorithms of the Long Term Evolution (LTE) layer 2 (L2) protocol processing on an ARM based mobile hardware platform. Furthermore, we investigate the applicability of a single ARM processor combined with a traditional hardware acceleration concept for the significantly(More)
In this paper we analyze the potential of using scratchpad memory in embedded devices to accelerate the operation of the L4/Fiasco microkernel affecting basically all applications on top of the kernel including virtualization software. We examine several low-level L4 system calls using a virtual prototype of Infineon's S-GOLD® platform for mobile(More)
In this paper we present a new on-the-fly hardware acceleration approach, based on a smart Direct Memory Access (sDMA) controller, for the layer 2 (L2) downlink protocol stack processing in Long Term Evolution (LTE) and beyond mobile devices. We use virtual prototyping in order to simulate an ARM1176 processor based hardware platform together with the(More)
In this paper we investigate hardware implementations of ciphering algorithms, SNOW 3G and the Advanced Encryption Standard (AES), for the acceleration of the protocol stack layer 2 in the 3G Long Term Evolution (LTE). This analysis is based on timing requirements from execution time measurements in a simulated mobile phone platform, where we apply data(More)
In this paper we present a new hardware/software co-design methodology for embedded systems, where software components written in Specification and Description Language (SDL) execute on a soft-model of a hardware platform, a so called Virtual Prototype (VP). The proposed approach enables fast exploration of different hardware and software design options at(More)
In this paper, we present different acceleration concepts for the Robust Header Compression version 2 (ROHCv2) algorithms in Long Term Evolution (LTE) handsets. First, we explore the potential performance improvements and energy savings by adopting scratchpad memories at various sizes. Second, dedicated hardware accelerators with different data transfer(More)
This article provides a detailed profiling of the layer 2 (L2) protocol processing for 3G successor Long Term Evolution (LTE). For this purpose, the most processing intensive part of the LTE L2 data plane is executed on top of a virtual ARM based mobile phone platform. The authors measure the execution times as well as the maximum data rates at different(More)
In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data plane processing of the LTE protocol stack layer 2 (L2) in downlink direction. For this purpose, a hybrid design approach is adopted allowing first investigations of future mobile phone(More)
The optimization of power consumption plays a key role in the design of a cellular system: Increasing data rates together with high mobility represent a constantly growing design challenge because advanced algorithms are required with a higher complexity, more chip area and increased power consumption which contrast with limited power supply. In this(More)