Sayed Masoud Sayedi

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This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow(More)
This paper presents a high-speed and pipelined bit-parallel multiplier over binary finite fields for elliptic curve cryptosystems. The architecture of this multiplier is based on a parallel structure and multiplication by 2, so that the two inputs apply to the circuit simultaneously and in parallel form. Furthermore, the structure of the proposed circuit is(More)
A log-domain current-mode true RMS-to-DC converter based on a novel synthesis of a simplified current-mode low pass filter and a two-quadrant squarer/divider is presented. The circuit employs floating gate MOS (FG-MOS) transistors operating in weak inversion region. The converter features low power(<1.5uW), low supply voltage (0.9V), two quadrant input(More)
This study presents a dual-edge triggered static scanable flip-flop suitable for low-power applications. The proposed circuit deploys reduced swing-clock and swing-data to manage dynamic power. Furthermore, it employs clockand power-gating during idle mode to eliminate dynamic power and reduce static power, while retaining its state. The static structure of(More)
In this paper an efficient high-speed architecture of Gaussian normal basis multiplier over binary finite field GF(2) is presented. The structure is constructed by using regular modules for computation of exponentiation by powers of 2 and low-cost blocks for multiplication by normal elements of the binary field. Since the exponents are powers of 2, the(More)
In this paper a 16-bit radix-4 pipelined divider implemented in a modified version of D<sup>3</sup>L family structure is presented. Performance of the circuit is evaluated and presented at different simulation corners. The results show that, compared with its dynamic version, the proposed circuit has lower power consumption and higher speed. Latency of the(More)
A new pixel architecture for the use in a multitask digital vision chip is presented. The architecture is based on SIMD parallel processing, and it is configurable to perform different binary image processing operations in high speed and with low power consumption. The proposed circuit can output the result in each period of its operating frequency, which(More)