Saumitra Raj Mehrotra

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Figure 1. I D-V G plot obtained for a 3.1 nm × 3.1 nm, [100] square SiNW with GAA oxide using 3D OMEN for different Lc and ToB (without DIBL adjustment). At Lc=10nm, results from 2 methods are in close agreement. Figure 2. (a) 3D GAA SiNW MOSFET. Lc shows the gate/channel length. A 2D slice (one unitcell long) from this part is taken for ToB simulation. S(More)
—The performances of ultrascaled SiGe nanowire field-effect transistors (NWFETs) are investigated using an atomistic tight-binding model and a virtual crystal approximation to describe the Si and Ge atoms. It is first demonstrated that the band edges and the effective masses of both relaxed and strained SiGe bulk are accurately reproduced by our model. The(More)
Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (E b) and of active channel area (S) with gate bias(More)
— As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (L g) are scaled to lengths shorter than L g < 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that(More)
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed(More)
The effect of diameter variation on electrical characteristics of long-channel InAs nanowire metal-oxide-semiconductor field-effect transistors is experimentally investigated. For a range of nanowire diameters, in which significant band gap changes are observed due to size quantization, the Schottky barrier heights between source/drain metal contacts and(More)
Nanostructures have attracted a great deal of attention because of their potential usefulness for high density applications. More importantly, they offer excellent avenues for improved scaling beyond conventional approaches. Less attention has been paid to their intrinsic potential for distinct circuit applications. Here we discuss how a combination of 1-D(More)
— We propose and analyze a high-current III-V transistor design using electron transport in the Γ-and L-valleys of (111) GaAs. Using sp 3 d 5 s * empirical tight-binding model for band-structure calculations and the top-of-the-barrier transport model, improved drive current is demonstrated using L-valley transport in a strained GaAs channel grown on an(More)
Introduction: SiGe pMOSFETs show considerable improvements in device performance due to the smaller hole effective mass exhibited by Ge.Further improvement in device performance can be obtained by growing pseudomorphically compressively strained SiGe on Si. Despite a lattice mismatch of ~4% between Si and Ge, researchers have been recently able to fabricate(More)