Saumitra Raj Mehrotra

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As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (L g) are scaled to lengths shorter than L g < 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that(More)
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed(More)
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This work focuses on the determination of the valid device domain for the use of the Top of the barrier (ToB) model to simulate quantum transport in nanowire MOSFETs in the ballistic regime. The presence of a proper Source/Drain barrier in the device is an important criterion for the applicability of the model. Long channel devices can be accurately modeled(More)
Nanostructures have attracted a great deal of attention because of their potential usefulness for high density applications. More importantly, they offer excellent avenues for improved scaling beyond conventional approaches. Less attention has been paid to their intrinsic potential for distinct circuit applications. Here we discuss how a combination of 1-D(More)
Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (E b) and of active channel area (S) with gate bias(More)
The performances of ultrascaled SiGe nanowire fieldeffect transistors (NWFETs) are investigated using an atomistic tight-binding model and a virtual crystal approximation to describe the Si and Ge atoms. It is first demonstrated that the band edges and the effective masses of both relaxed and strained SiGe bulk are accurately reproduced by our model. The(More)
We propose and analyze a high-current III-V transistor design using electron transport in the Γand L-valleys of (111) GaAs. Using sp3d5s∗ empirical tight-binding model for band-structure calculations and the top-of-the-barrier transport model, improved drive current is demonstrated using L-valley transport in a strained GaAs channel grown on an (111) InP(More)
bstract—The thermoelectric power-factor PF) and efficiency ZT) of GaAs nanowires NWs) can be improved by i) choosing a proper wire growth and channel orientation, ii) by applying uniaxial tensile stress, and iii) suitable wire cross-section size. In this work we study the impact of these three factors on the PF and the ZT. Tensile stress, channel direction(More)
Introduction: SiGe pMOSFETs show considerable improvements in device performance due to the smaller hole effective mass exhibited by Ge.Further improvement in device performance can be obtained by growing pseudomorphically compressively strained SiGe on Si. Despite a lattice mismatch of ~4% between Si and Ge, researchers have been recently able to fabricate(More)