Saumitra Mehrotra

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Figure 1. I D-V G plot obtained for a 3.1 nm × 3.1 nm, [100] square SiNW with GAA oxide using 3D OMEN for different Lc and ToB (without DIBL adjustment). At Lc=10nm, results from 2 methods are in close agreement. Figure 2. (a) 3D GAA SiNW MOSFET. Lc shows the gate/channel length. A 2D slice (one unitcell long) from this part is taken for ToB simulation. S(More)
—The performances of ultrascaled SiGe nanowire field-effect transistors (NWFETs) are investigated using an atomistic tight-binding model and a virtual crystal approximation to describe the Si and Ge atoms. It is first demonstrated that the band edges and the effective masses of both relaxed and strained SiGe bulk are accurately reproduced by our model. The(More)
— As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (L g) are scaled to lengths shorter than L g < 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that(More)
The effect of diameter variation on electrical characteristics of long-channel InAs nanowire metal-oxide-semiconductor field-effect transistors is experimentally investigated. For a range of nanowire diameters, in which significant band gap changes are observed due to size quantization, the Schottky barrier heights between source/drain metal contacts and(More)
Nanostructures have attracted a great deal of attention because of their potential usefulness for high density applications. More importantly, they offer excellent avenues for improved scaling beyond conventional approaches. Less attention has been paid to their intrinsic potential for distinct circuit applications. Here we discuss how a combination of 1-D(More)
Introduction: SiGe/Si core/shell nanowire (NW) devices are promising candidates for the future generation MOSFETs providing better channel control and hole mobility [1-4]. These core-shell devices can be exploited both as p-and n-type devices [3]. The Si shell improves the semiconductor-oxide interface and enhances the device performances [1, 3]. The(More)
— We propose and analyze a high-current III-V transistor design using electron transport in the Γ-and L-valleys of (111) GaAs. Using sp 3 d 5 s * empirical tight-binding model for band-structure calculations and the top-of-the-barrier transport model, improved drive current is demonstrated using L-valley transport in a strained GaAs channel grown on an(More)
  • Seung Hyun Park, Mathieu Luisier, Benjamin Haley, Samarth Agawal, Abhijeet Paul, Muhammad Usman +17 others
  • 2011
ii This thesis is dedicated to my parents. iii ACKNOWLEDGMENTS I would like to thank my advisor, Professor Gerhard Klimeck who gave me the opportunity to work on researches with valuable insights and all the required resources since the beginning of my graduate year. I also thank to my co-advisor, Professor Lloyd C. L. Hollenberg for providing novel ideas(More)
bstract—The thermoelectric power-factor PF) and efficiency ZT) of GaAs nanowires NWs) can be improved by i) choosing a proper wire growth and channel orientation, ii) by applying uniaxial tensile stress, and iii) suitable wire cross-section size. In this work we study the impact of these three factors on the PF and the ZT. Tensile stress, channel direction(More)
— This work presents a comprehensive analysis of the SiGe band structure using a Tight-Binding based approach within the virtual crystal approximation. We analyze the material properties of bulk relaxed SiGe and biaxially compressed strained systems. The simulation approach has been benchmarked against experimental data wherever possible. We further(More)