Satoshi Uemori

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This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable. key(More)
A series of the titled compounds was synthesized and tested for anti-Helicobacter pylori activities. We discovered Y-34867 having the most potent activity against Helicobacter pylori among the quinolones tested along with high photostability. Furthermore, Y-34867 showed an excellent therapeutic effect in the experimental Helicobacter pylori infected(More)
This paper describes a time-to-digital converter (TDC) architecture with fine time resolution, self-calibration and self-testing, and these features are realized by the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit for linearity improvement. (3) Stochastic architecture for fine time resolution. (4)(More)
This paper proposes an improved method of background calibration that reduces production testing time of mixedsignal ICs. Production testing time typically consists of “calibration convergence time” + “functional testing time after calibration convergence”. The method that is proposed here reduces average calibration convergence time. This method does not(More)
This paper describes an algorithm for generating test signals to efficiently test the linearity of ADCs. Linearity is an important testing item for ADCs, and it takes a long time (hence is costly) to test low-sampling-rate, high-resolution ADCs. We here propose to generate a test signal consisting of multiple sine waves, to precisely test the linearity for(More)
This paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However it suffers from nonlinearity, and hence needs calibration; conventional background(More)
This paper describes the architecture (circuit design) and principles of operation of sigma-delta (ΣΔ) time-todigital converters (TDC) for high-speed I/O interface circuit test applications; they offer good accuracy with short test times. In particular, we describe multi-bit ΣΔ TDC architectures for fast testing. However, mismatches among delay cells in(More)
This paper describes the architecture and principles of operation of sigma-delta ( ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity.(More)
This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and(More)