Satish L. Rege

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This paper evaluates the effect of cost and performance tradeoffs on memory system hierarchies achieved by varying the total amount of memory at any two adjacent levels. The hierarchy is analyzed in a multiprogramming mode by using a two server cyclic queuing model. As an example, a two level hierarchy of Bipolar, MOS and a three level hierarchy of Bipolar,(More)
This paper discusses the design and use o f system-building modules o f about minicomputer complexity. These modules (CMs), are intended t o f a c i l i t a t e t h e design o f the f u l l range o f digital s y s t e m s needed t o carry out current and f u t u r e computational tasks. Module sets f o r computer system design are becoming increasingly(More)
This work addresses the issue of exploring design alternatives for data part (as contrasted with control part) implementations for digital systems using register transfer (RT) level components. Certain assumptions are made regarding the RT level of design, and a model for data part designs is postulated. It is shown that the number of possible designs is(More)
The architecture and With the advent of fiber implementation presented distributed data interface in this paper are for the (FDDI) technology, Digital DEC FDDIcontroller 400, saw the need to define Digital's high-performance, an architecture for a XMI-to-FDDI adapter known high-performance adapter as DEMFA. This adapter that could transmit data provides an(More)
In CCD memory systems a tradeoff exists between the frequency at which the memory system is operated and the power dissipation. The higher the frequency of operation, the lower is the service time and the higher is the power dissipation. A close look at the initial cost of the CCD memory system and the cost of maintaining these memory systems will show that(More)
This paper discusses the computer memory system design implications of different CCD devices, such as Circulating Shift Register, Serial Parallel Serial, and Line Addressable Organizations. The performance of the memory using these devices is evaluated in a stand alone mode using a single server queuing model, and as a buffer between the disk and main(More)
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