Satish K. Bandapati

Learn More
In this paper a number of 4-bit, 8-operation arithmetic logic units (ALUs) are designed using the delay-insensitive NULL Convention Logic (NCL) paradigm, and are characterized in terms of speed and area. Both dual-rail and quad-rail, pipelined and non-pipelined versions are developed, and the tradeoffs and design considerations for each are discussed.(More)
FOR THE PAST TWO DECADES, digital design has focused primarily on synchronous, clocked architectures. However, because clock rates have significantly increased while feature size has decreased, clock skew has become a major problem. To achieve acceptable skew, high-performance chips must dedicate increasingly larger portions of their area to clock drivers,(More)
  • 1