Satish K. Bandapati

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In this paper a number of 4-bit, 8-operation arithmetic logic units (ALUs) are designed using the delayinsensitive NULL Convention Logic (NCL) paradigm, and are characterized in terms of speed and area. Both dualrail and quad-rail, pipelined and non-pipelined versions are developed, and the tradeoffs and design considerations for each are discussed.(More)
26 0740-7475/03/$17.00 © 2003 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers FOR THE PAST TWO DECADES, digital design has focused primarily on synchronous, clocked architectures. However, because clock rates have significantly increased while feature size has decreased, clock skew has become a major problem. To achieve(More)
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