Satish Grandhi

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Traditional logic synthesis methodologies are driven by timing, power, and area constraints. However, due to aggressive technology shrinking and lower power requirements, circuit reliability is fast turning out to be yet another major constraint in the VLSI design flow. Soft errors, which traditionally affected only the memories, are now also resulting in(More)
With the advent of deep submicron CMOS technology, process parameter statistical variations are increasing resulting in unpredictable device behaviour. The issue is even aggravated by low power requirements which are stretching transistor operation into near/sub threshold regime. Consequently, traditional delay models fail to accurately capture the circuit(More)
The low reliability of advanced CMOS devices has become a critical issue that has to be considered in the digital IC design flow. This paper introduces a design time methodology to address and improve the reliability of combinational circuits. The key idea is to employ local transformation rules, a methodology that were extensively used for area, delay, and(More)
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